Conventionally, there is well known a multi-level NAND flash memory in which each memory cell can retain data having at least two bits. It is also well known that flag data indicating the number of bits of the data each memory cell stores (for example, whether the memory cell stores one bit data or two bit or more data) is used in the multi-level NAND flash memory. For example, Japanese Patent No. 3935139 discloses the technique of the multi-level NAND flash memory. During data read, a proper read operation can be performed by previously confirming the flag data. In the NAND flash memory, an error correction circuit (ECC circuit) is usually provided on the assumption that a defective bit exists. For example, Jpn. Pat. Appln. KOKAI Publication No. 2009-087491 discloses the ECC circuit. The maximum number of defective bits permitted in each one page is previously determined.
However, when the defective bits are intensively generated in a region where the flag data is stored, the correct read is hardly performed.